The present invention relates to integrated logic circuits and, more particularly, to a CMOS input voltage level detector circuit.
A CMOS integrated circuit is a type of MOSFET integrated circuit which includes both N-channel and P-channel transistors. Furthermore, it is advantageous to increase the functionality of a CMOS integrated circuit without increasing the number of external pins or terminals. Also, it is almost always advantageous to have a circuit wherein its input can provide more than one distinct function.
Prior art has made several attempts at minimizing the number of external pins of an integrated circuit. One attempts has been the sharing of external pins as both an input and output. Another approach for minimizing the number of pins is the use of a trinary input circuit at an input pin. The trinary circuit provides two outputs which provide different output states depending upon whether a logic low or high is applied to the input pin or whether the input pin is left floating. However, this approach is not desirable in CMOS circuitry since floating inputs are not recommended.
Another approach for minimizing the number of pins utilizes circuitry on the integrated circuit to detect when a voltage applied to an input pin is substantially greater than the power supply voltage whereby the detection of such a large voltage forces the circuitry on integrated circuit to function differently than under normal operating conditions. Prior art has implemented this latter approach by connecting an input pin not only to the inputs of conventional logic circuitry, but also to the gate electrode of an on-chip enhancenment mode transistor having a threshold voltage higher than the power supply voltage so that the transistor will remain nonconductive when a normal logic one or logic zero is applied to the input pin, but become conductive when a voltage substantially greater than that of the power supply is applied to the input. However, the application of an unusually high voltage to an input pin is impractical because there is typically an on chip diode connected between the input pin and the CMOS integrated circuit's power supply node. Therefore, the diode will prevent the input voltage from being taken to voltage substantially more positive than the most positive power supply of the circuit.
Hence, a need exists for a CMOS level detector circuit that will increase the functionality of an integrated circuit without increasing the number of external pins or terminals.